1. Field of the Invention
The present invention relates to a chip enable control circuit which controls a chip enable (CE) signal for a memory in a system including the memory and a central processing unit (CPU) with a cache memory, a memory control circuit which includes the chip enable control circuit, and a data processing system which includes the memory control circuit.
2. Description of the Related Art
A system which includes a CPU with a cache memory and a flash memory is disclosed in, for example, the Japanese Patent Application Kokai (Laid-Open) Publication No. 8-76875 (patent document 1).
FIG. 11 is a block diagram showing the construction of a conventional system which includes a CPU 1, a cache controller 2, a cache memory 3, a flash memory controller 4a, and a flash memory 5. In this system, the CPU 1 fetches code data from the cache memory 3 via the cache controller 2 or code data from a common bus, and performs an operation according to the fetched code data and other operation. When the CPU 1 reads a code from a common memory, the cache controller 2 generates a signal HADDRI indicating an address of the flash memory 5, a signal HTRANSI indicating whether an address is an enable level or disable level, and a signal HBURSTI indicating the number of transfers, and outputs them to the address side common bus.
FIG. 12 is a block diagram showing the construction of a conventional flash memory controller 4a. The flash memory controller 4a includes an address decoder circuit 6, an address/read enable (RE) generating circuit 7, and a data output circuit 8. The address decoder circuit 6 receives the signals HADDRI, HTRANSI, HBURSTI, and HREADYI (which indicates the end of transfer of a previous cycle) of the address side common bus, and outputs a startup request signal S_REQ and an address ADDR. The address/RE generating circuit 7 receives the startup request signal S_REQ and the address ADDR, outputs a read enable signal (RE signal) and an address signal Flash(A) to the flash memory 5, and outputs an output request signal O_REQ to the data output circuit 8. In FIG. 12, the input terminal T(CE) for a CE signal of the flash memory 5 is connected to an L level (GND), and the flash memory 5 is brought to an operable state (activated state). The output request signal O_REQ outputted from the address/RE generating circuit 7 and data Flash(D) outputted from the flash memory 5 are inputted to the data output circuit 8. The data output circuit 8 outputs a signal HRDATAI to the data side common bus and outputs a signal HREADYO to the address side common bus.
FIG. 13 is a diagram showing operating waveforms when a cache miss hit occurs in the above-mentioned conventional system, i.e., in a case where a CE signal is always an enable level (set to L level) and CE control is not performed. In FIG. 13, CPUCLK denotes the operating clock of the CPU 1, HCLK denotes a clock generated by the CPU 1, MEMCLK denotes an operating clock of the flash memory 5, and Flash0 (D) and Flash1 (D) denote data outputted from the flash memory 5. When an address IA is outputted from the CPU 1 (time t131), the cache controller 2 outputs signals HADDRI, HTRANSI, and HBURSTI to the address side common bus (time t132). When the signals HADDRI, HTRANSI, HBURSTI, and HREADYI are signals to be used for accessing the flash memory 5, the address decoder circuit 6 of the flash memory controller 4a generates a startup request signal S_REQ in synchronization with the clock HCLK by the use of the signals HADDRI, HTRANSI, HBURSTI, and HREADYI, and holds the signal HADDRI which is an address value of the flash memory 5. The address/RE generating circuit 7 receives the startup request signal S_REQ and the held address value HADDRI, and generates an address Flash(A) and an RE signal (times t133, t134). The flash memory 5 outputs data Flash(D) relating to the address Flash(A) in synchronization with the clock MEMCLK (time t135). The data output circuit 8 waits for an output request (O_REQ in FIG. 12) generated by the address/RE generating circuit 7, and outputs the data HRDATAI relating to the output request to the common bus (time t136). The data HRDATAI outputted to the common bus is inputted as data ID to the CPU 1 via the cache controller 2 (time t137)
However, since the conventional flash memory controller 4a shown in FIG. 12 does not perform the CE control, i.e., the CE terminal T(CE) of the flash memory 5 is connected to the ground (GND), the flash memory 5 is activated even for such a period of cache hit which is a period during which the data of the flash memory 5 is not used, which results in raising the problem of causing an increase in power consumption.
Moreover, when an already-existing CE control is applied to the conventional flash memory controller 4a shown in FIG. 12, there is presented a problem that an increase in cycle at the time of cache miss hit markedly degrades the performance of the system. This problem will be described below.
FIG. 14 is a diagram for describing a degradation in the performance of the system and is a diagram showing operating waveforms at the time of cache miss hit in the conventional system, to which an already-existing CE control for changing the CE signal in FIG. 12 to an L level (enable level) or an H level (disable level) is applied. As shown in FIG. 14, if an address IA(a0) is outputted when the CE signal of the flash memory 5 is the H level, i.e., in the mode of low power consumption (time t141), the cache controller 2 outputs the signals HADDRI(a0) and other signals (time t142), and the flash memory controller 4a sets the CE signal to the L level (enable level) (time t143), supplies the flash memory 5 with an address Flash(A) (time t144), and sets the RE signal to the L level (read enable) (time t145). However, in order to enable the flash memory 5 to be used after the CE signal inputted to the flash memory 5 is set to the L level (time t143), it is necessary to wait for the CE setup time of the flash memory 5 to pass. Therefore, as in the case of the already-existing CE control, when the flash memory controller 4a sets the flash memory 5 to the low power consumption mode (i.e., sets CE signal to the H level) every time a cache hit occurs, it is necessary to wait for the CE setup time of the flash memory 5 to pass every time a cache miss hit occurs. This becomes the cause of degrading the performance of the system.